Cerberus “Zeus” is a security-hardened, formally verified CPU core with countermeasures for:
- Fault attacks
- Side-channel attacks
- Logical attacks
It is highly configurable and there are options for:
- A dual lock-step version (improved resistance to fault attacks including electromagnetically-induced faults)
- 3 or 5 stage pipeline
It can be deployed on FPGA for test and development as well as ASIC and has an AXI interface for easy integration.
A set of common peripherals are also available for the core, including:
- RISC-V compliant platform level interrupt controller (PLIC)
- I2C master
- (Q)SPI master and slave
Additional security IP
Additional security-related IP is also available:
- True Random Number Generator (TRNG)
- Encrypting/authenticating cache
- Elliptic Curve Cryptography accelerator
- Active shield for protection against probing attacks
The core is supported by a full set of software tools:
- A GCC 10 and LLVM 11 compiler and toolchain with support for added extensions
- A C/C++ SDK including accelerated cryptographic algorithm support
- Debug support (for development use only - hardware support must not be deployed in a final product)
As the core is compliant with the RISC-V RV32 ISA, any code suitable for this ISA will run on Zeus.
A product overview is coming soon. Access to full documentation requires an NDA.