Zeus hardened RISC-V core

Cerberus Zeus logo

Overview

Cerberus “Zeus” is a security-hardened, formally verified CPU core with countermeasures for:

  • Fault attacks
  • Side-channel attacks
  • Logical attacks

It is fully compliant with the RISC-V RV32IMC ISA, with optional support for the experimental bitmanip (B) extension and scalar cryptography extension.

It is highly configurable and there are options for:

  • A dual lock-step version (improved resistance to fault attacks including electromagnetically-induced faults)
  • 3 or 5 stage pipeline

It can be deployed on FPGA for test and development as well as ASIC and has an AXI interface for easy integration.

Peripheral support

A set of common peripherals are also available for the core, including:

  • RISC-V compliant platform level interrupt controller (PLIC)
  • Timers
  • Watchdog
  • UART
  • I2C master
  • (Q)SPI master and slave

Additional security IP

Additional security-related IP is also available:

Software support

The core is supported by a full set of software tools:

  • A GCC 10 and LLVM 11 compiler and toolchain with support for added extensions
  • A C/C++ SDK including accelerated cryptographic algorithm support
  • Debug support (for development use only - hardware support must not be deployed in a final product)

As the core is compliant with the RISC-V RV32 ISA, any code suitable for this ISA will run on Zeus.

More details

A product overview is coming soon. Access to full documentation requires an NDA.