Cerberus presents at Bristol RISC-V Meetup

picture of Bristol RISC-V meetup logo

RISC-V processor presentation:

We presented our motivation and a brief technical progress update of our research project to design a secure CPU at this month’s RISC-V Meetup in Bristol.

A brief introduction to RISC-V

RISC-V is an open standard CPU Instruction Set Architecture (ISA). An ISA is a specification of how a CPU should operate (e.g. the instruction set, registers, etc.) but it is not an implementation.

There are now a number of open source 32 and 64 bit implementations that follow this ISA such as:

These implementations are optimised for a particular feature such as power, silicon area or performance.

There are also a number of commercial implementations now available as well that can integrated to form the basis of System-on-Chip designs. For example SiFive are a well-known supplier and integrator of RISC-V devices.

Cerberus have developed their own implementation of the RISC-V ISA (a 32-bit RV32IM class) that is focussed on security as part of an academic research project.


You can find the PDF of the presentation here